1. Field of the Invention
The present invention relates to methods for manufacturing a semiconductor device such as a CMOS transistor, and more particularly to a method for manufacturing a semiconductor device suitable for designing micro-transistors in LSI manufacturing techniques.
2. Description of the Related Art
To manufacture a CMOS transistor, such a method has been employed which includes the step of forming extension layers, followed by the step of forming sources and drains and then an annealing step for activating implanted ion dopant. However, by this method, it is difficult to sufficiently activate the sources, the drains, and the gates while providing abrupt extension layers with reduced overlaps therebetween.
In this context, studies have been recently made on a method for carrying out two-step annealing in the art. According to this method, the step of forming sources and drains is first carried out, followed by the step of rapid high-temperature annealing, thereby activating implanted dopants. The subsequent step of forming extension layers is performed, followed by the step of lower temperature annealing than the first annealing, thereby activating the implanted dopants again. This ensures a sufficient activation in the sources, the drains, and the gates as well as abruptness of the extension layers.
Now, the method of carrying out the two-step annealing is explained with reference to the attached drawings. FIG. 8 is a view illustrating the layout of a transistor. FIGS. 9A and 9B to FIGS. 12A and 12B are cross-sectional views of a semiconductor device in various stages of manufacture shown in the order in which they appear in the prior art method. FIGS. 9A, 10A, 11A, and 12A are cross-sectional views taken along the line III—III in FIG. 8, while FIGS. 9B, 10B, 11B, and 12B are cross-sectional views taken along the line IV—IV in FIG. 8.
In this prior art manufacturing method, as shown in FIG. 9A, STI (Shallow Trench Isolation) is employed to selectively form a device isolation insulator film 22 on a semiconductor substrate 21. Then, as shown in FIGS. 9A and 9B, a gate insulator film 23 and a gate electrode 24 are formed within a device active region defined by the device isolation insulator film 22 such that their both ends extend onto the device isolation insulator film 22. Thereafter, a SiO2 film is formed on the entire surface and etch-backed by anisotropic etching, thereby forming sidewalls 25. Then, using as a mask the gate electrode 24 and the sidewalls 25, an ion dopant is implanted into the device active region, thereby forming a source 26S and a drain 26D therein, as shown in FIG. 9B. Then, an annealing step is carried out to activate the implanted ion dopant.
Then, as shown in FIGS. 10A and 10B, the sidewalls 25 are removed.
Then, as shown in FIGS. 11A and 11B, a SiO2 film 27 and a SiN film 28 are sequentially formed on the entire surface.
Thereafter, as shown in FIGS. 12A and 12B, the layered stack of the SiO2 film 27 and the SiN film 28 is etch-backed, thereby forming an offset film 29. Then, as shown in FIG. 12B, using as a mask the offset film 29 and the gate electrode 24, an ion dopant is implanted into the device active region, thereby forming extension layers 30 so as to overlap the source 26S and the drain 26D. Then, an annealing step is carried out to activate the implanted ion dopant.
As shown in FIGS. 10A and 10B, in the method for manufacturing a semiconductor device by employing the aforementioned two-step annealing, the sidewalls 25 are removed after the source 26S and the drain 26D have been formed. The sidewalls 25 are removed typically by means of wet treatment. At this stage, in the device active region, since the gate insulator film 23 is formed on the semiconductor substrate 21, the insulator film itself very thin in thickness is thus less prone to being retreated. On the other hand, on the device isolation insulator film 22, the gate insulator film 23 extends onto the device isolation insulator film 22, where the thickness of the insulator film is the sum of the thickness of the gate insulator film 23 and that of the device isolation insulator film 22. Thus, the gate insulator film 23 and the device isolation insulator film 22 are apt to retreat. As shown in FIG. 10A, a small amount of the surface of the device isolation insulator film 22 is stripped away and the dimensions of the gate insulator film 23 are reduced. Consequently, in the design rules for gates of about 100 nm or less in length, problems will rise with the gate electrode 24 on the gate insulator film 23 such as toppling, deformation, or peeling.
Furthermore, in the aforementioned prior art manufacturing method, notches are formed between the offset film 29 and the semiconductor substrate 21 to form the extension layers 30. This causes the gate insulator film 23 to be easily retreated upon forming the notches, thereby further reducing the dimensions of the gate insulator film 23 as shown in FIG. 12A. Thus, the aforementioned problems become further noticeable.